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Dual 50MHz to 1000MHz High-Linearity,
Serial/Analog-Controlled VGA
Table 1. Control Logic
AA_SP
0
1
ANALOG ATTENUATOR
Controlled by external control voltage
Controlled by on-chip DAC
D/A CONVERTER
Disabled
Enabled (DAC output voltage shows on A_VCTL__ pins);
DAC uses on-chip voltage reference
Table 2. Operating Modes
Applications Information
RESULT
All on
AMP1 off
AMP2 on
AMP1 on
AMP2 off
All off
V CC (V)
5
3.3
5
3.3
5
3.3
5
3.3
AMP_SET
0
1
0
1
0
1
0
1
PD_1
0
0
1
1
0
0
1
1
PD_2
0
0
0
0
1
1
1
1
Operating Modes
The device features an optional +3.3V supply volt-
age operation with reduced linearity performance. The
AMPSET pin needs to be biased accordingly in each
mode, as listed in Table 2. In addition, the driver amplifiers
can be shut down independently to conserve DC power.
See the biasing scheme outlined in Table 2 for details.
SPI Interface and Attenuator Settings
The attenuators can be programmed through the 3-wire
SPI/MICROWIRE K -compatible serial interface using
Driver Amplifier
Each path of the device includes a high-performance
driver with a fixed gain of 24dB. The driver amplifier
circuits are optimized for high linearity for the 50MHz to
1000MHz frequency range.
MSB
5-bit words. Fifty-six bits of data are shifted in MSB first
and are framed by CS . The first 28 bits set the first atten-
uator and the following 28 bits set the second attenuator.
When CS is low, the clock is active and data is shifted on
the rising edge of the clock. When CS transitions high,
the data is latched and the attenuator setting changes
(Figure 1). See Table 3 for details on the SPI data format.
LSB
DAT
DN
D(N-1)
D1
D0
CLK
t CW
CS
t CS
t CH
t ES
t EWS
t EW
NOTES : DATA ENTERED ON CLOCK RISING EDGE.
ATTENUATOR REGISTER STATE CHANGE ON CS RISING EDGE.
N = NUMBER OF DATA BITS.
D0 IS AN ADDRESS BIT, D1/DN ARE DATA BITS (WHERE N P 20).
Figure 1. SPI Timing Diagram
MICROWIRE is a trademark of National Semiconductor Corp.
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